The ever-increasing complexity and performance requirements of portable electronic devices call for effective system-level power management in Integrated circuits (ICs). Having one or more switchable power domains in core-logic is a well-known low-power methodology that is employed for ICs in portable electronic devices. When a supply of a specific power domain is powered down, the outputs of that power-domain serving as inputs to IO (input/output) circuits are no longer valid and these IO circuits need to be tri-stated to avoid possible leakage current.
An IO circuit drives/receives signals on a pad to interface with the outside world. If the IO circuit is not properly tri-stated, it results in high leakage currents (conduction currents) from the pad into the IO circuit. A similar condition results when the IO supply voltage is powered up or down, while the pad is held at a logic-HIGH.
A typical example of this is a DRAM (Dynamic random-access memory) controller IC used in conjunction with a DDR3 SDRAM (Synchronous dynamic random access memory). The DDR3 SDRAM JEDEC standard provides an ultra-low power DRAM feature using a RESET pin. The DRAM controller IC includes an IO circuit which is interfaced to the DDR3 SDRAM through a pad. This pad serves as the RESET pin of the DRAM controller.
The ultra-low power feature allows turning off all interface signals and preserving DRAM content by holding RESET pin (or the pad) at logic high, putting DRAM in self refresh mode. This becomes a very attractive feature in low power application space since it allows the complete power down of DRAM controller IC when the DRAM controller IC is not being accessed, with only RESET pin being held high. To enable this ultra-low power state, an IO power supply connection for the DRAM controller and the DDR3 SDRAM are separated on board. The sharing of the same IO power supply would power down the DDR3 SDRAM as well, thus clearing its content.
When the IO power supply to the DRAM controller is powered down, and the RESET pin is held high, a leakage current flows from the RESET pin (the pad) to the IO circuit in the DRAM controller when the IO circuit is not properly tri-stated. Because of this condition, the RESET pin undergoes a glitch. This resets the DDR3 SDRAM. The overhead of re-initializing the DDR3 SDRAM at every power cycle is significant.